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In this work, up to 80 Gbit/s monolithically integrated clock and data recovery (CDR) circuits with 1:2 demultiplexer are developed. The integrated circuits are manufactured using an InP double heterojunction bipolar transistor (DHBT) technology, featuring cut-off frequency values of more than 250 GHz. The outstanding and (to some extent) record achievements throughout the work make an essential contribution to the development of future optical telecommunication networks operating at 80 Gbit/s.
Umfang: VI, 167 S.
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Makon, R. 2006. InP DHBT-based clock and data recovery circuits for ultra-high-speed optical data links. Karlsruhe: KIT Scientific Publishing. DOI: https://doi.org/10.5445/KSP/1000004568
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Veröffentlicht am 27. Juni 2006
Englisch
179
| Paperback | 978-3-86644-045-6 |